Apparatus for performing division and base conversion

ABSTRACT

A method of representing numerical information in binary form wherein a plurality of dot patterns are established on a data medium and numerical weighting is given to each dot pattern by selectively joining dot pairs of the pattern with essentially straight lines, and apparatus for reading numerical information in the form set out above including apparatus which utilizes electronic pulses or sensing scanners for interrogating the space between dot pairs which can have lines drawn therebetween in order to determine the numerical weighting of a numerical dot pattern.

United States Patent [191 Barnes [11] 3,752,964 [4 1 Aug. 14, 1973 APPARATUS FOR PERFORMING DIVISION AND BASE CONVERSION Inventor: William S. Barnes, 912 Greenfield Court, Mt. Prospect, I11. 60056 Filed:

Appl. No.: 68,772

Sept. 1, 1970 Related [1.8. Application Data Division of Ser. No. 625,913, March 7, 1967, Pat. No.

US. Cl 235/92 CA, 307/224 Int. Cl. G06!!! 3/00, H031: 13/00 Field of Search 307/224 R, 220, 221;

328/42; 340/168 R, 146.3 Q, 146.3 Y, 146.3 R; 235/92 CC, 92 CA References Cited UNITED STATES PATENTS 1/1970 Kolell et a1 235/92 CA EEEBJ Primary Examiner-Thomas A. Robinson Attorney-Fryer, Tjensvold, Feix & Phillips [57] ABSTRACT A method of representing numerical information in binary form wherein a plurality of dot patterns are established on a data medium and numerical weighting is given to each dot pattern by selectively joining dot pairs of the pattern with essentially straight lines, and

9 Claims, 17 Drawing Figures RESET M Eli] Ra i559 PAIENIEDIus 14 ms SHEET 1 OF 6 QQLWLA I I I I 2 W22" CIRCUIT NETWORK FIG3 SOURCE GATE CIRCUIT NETWORK ill IL [L \W B 4 W 4 8 7 2 W 2 L 2 G L 7 b AA m U S T U R U I U RE N C A N C T C P E M O m 8 U R W R m 5 w cc G PATENIEIlAuc 14 m SHEET 3 (If 6 FIG. 6

FIG. 7

GATE CIRCUIT NETWORK PULSE GENERATOR MEANS BASE COUNTING CIRCUIT CONTROL CIRCUIT PATENTED MJB I4 I875 SHEET U 0F 6 CONTROL SCAN NUMBER SCAN FIG. 9

N A C s L 0 R T N O C TA B rIII E B III B l I 8 rIII B 1.!

UI o A A AF &1 i J NUMBER SCAN FIG. IO

PULSE GENERATOR MEANS BB A A BASE COUNTING CIRCUIT PATENIEmucMma 3352.964

SHEET 5 BF 6 FIG. ll

CONTROf v 77 79 Ufljjjj 055G 31F OPERATOR SWITCH U E] Uc FIG. :2

{ 5' mg RESET BIAS OFF REGISTER ON DELAY APPARATUS FOR PERFORMING DIVISION AND BASE CONVERSION This is a division of U.S. Pat. application Ser. No. 625,913; filed Mar. 7, 1967, now U.S. Pat. No. 3,559,170 dated Jan. 26, 1971.

BACKGROUND OF THE INVENTION ment. Numerous systems have been devised for accomplishing this task. In general these systems are adapted to specific applications and are unsuitable for some of the other applications. These systems may be classified as direct (use of a Teletype keyboard, pushbuttons, or switches which feed numbers directly into a computer or other automatic devices) and indirect (use of punched cards ortape, magnetic tape, special alphanumeric symbols on papers, etc.,which may be sensed by a data input device of the computer). The indirect means have an advantage over direct means in that the data may be prepared in advance, stored for future use, and, if legible, edited after preparation. For these reasons and others indirect means of data input maybe used for masses of data so large and computer pro grams so long that direct means would be impractical.

The methods now in use for preparing data for input to computers by indirect means have a number of defccts that limit their use in various ways. Some methods, such as those with magnetic tape, punched cards or tape, etc., produce data in a form which is either wholly or partially illegible so far as reading the data by eye is concerned, and supplementary apparatus for reading the data is usually necessary and provided.

In order to overcome the defect of illegibility various character recognition systems have been devised so that data may be presented in an alphanumeric form which may be read directly by a person or alternately by a machine. It isattempted in suchsystems to present the data in modified versions of the Hindu-Arabic numerals and sometimes in standard alphabetical characters. In these systems, there are varying requirements for precision in both position and shape of the symbols and in the structure and positioning of the reading device used by the machine. In some cases the structure of each symbol must be so formally precise as to necessitate the use of a machine to print it. In others, the requirements for structural precision of the characters are relaxed somewhat but are not eliminated entirely, i.e., there is notyet any system that can unfailingly read any recognizable alphanumeric character. The systems which are used to sense and read such alphanumeric characters vary both in complexity and in the requirements for precision. In general it may be saidthat the complexity and sophistication of such systems increases with a decrease in the requirements for precision in writing the alphanumeric characters so that one pays for an increase in ease of writing the characters by an increase in the complexity of the systems used to read the characters.

The use of such special equipment such as keypunches, special typewriters, etc., is frequently indicated by consideration of speed and efficiency in the preparation of data for input to computers. However, there might occur situations in which such equipment might not be available. The preparation of data would also be made easier if parts of it could be erased and modified by hand. In the case of many systems in use today, the requirements for precision are so great that the preparation of data by hand is totally out of the question, and the use of special equipment is absolutely necessary.

The use of numerals having shapes corresponding roughly to the shapes of Hindu-Arabic numerals has one other disadvantage. When a number is read into a digital computer, it is represented in the computer by the functional state of a circuit, specifically in digital computers by a state of a circuit consisting of a series of binary flip-flop circuits. A number, which originally was represented by a series of decimal (or quartal, octal, etc.) numerals, must be represented in the computer in such a way that arithmetic and other operations may be carried out. One method of representation frequently used isbinary coded decimal (or perhaps binary coded quartal, octal, -etc.). In this representation each decimal (quartal, octal, etc.) numeral of the original number is represented by a separate binary number. The more usual method is to represent the complete number as a single binary number. The numerical reading systems in use today do not, in general, read Hindu- Arabic numerals into a computer circuit in their binary representation. Each numeral is read into the computer circuit in a representation which depends on its unique structural characteristics and on the read system used. In general, no single algorithm can be used to convert the representations of all of the Hindu-Arabic numerals in such systems into their binary representations. Hence, unique circuit arrangements (or programmatic arrangements) must be made to convert each numeral into its binary representation. If, in addition, it is desired to represent a number written as a series of Hindu-Arabicnumerals as a single binary number, a further conversion arrangement is required. In order to avoid the disadvantages mentioned above, numerals and conventional alphabetic characters arenot used in this invention, and whatever disadvantages arise from this departure, they are felt to be minor when compared to the advantages, which will be made clear in the description which follows.

SUMMARY OF THE INVENTION It is an object of this invention to provide methods and apparatus for recording numerical data in the form of symbols which may be read directly by eye read by a'machine, written by hand, printed by a machine, and if necessary manually erased and rewritten. The form of the symbols chosenenables either a single numeral or a multidigit number to be written by the symbols and read directly as a single binary number. The means chosen have the additional advantages that the requirements for precision both in writing the numerals and in the positioning of the sensing elements in the reading means are substantially less than for most existing data reading systems. Since the numbers maybe read directly as binary numbers, the use of additional equipment for conversionof the numbers being read into binary numbers is avoided. A further outstanding characteristic possessed by the symbols used in this invention is that a person of ordinary intelligence will be able to learn how to read and write them with only a few minutes of instruction.

Since the symbols of the present invention are written for the purpose of being read electronically it is necessary to employ one of several possible means for writing the symbols so that they can be electronically detected. One such means is to write or print the symbols with electrically conducting ink or lead in designated positions on a prepared format. Use is then made of the change in electrical conductivity between various points on the format (data medium) produced by these symbols to accomplish the read operation. A second means is to make use of a contrast in some characteristic between the marks comprising the symbols and the background material on which they are written (data medium). For instance, a contrast between light and dark may be detected by a photo-cell or a contrast in magnetic susceptibility, which might occur if the lead or ink contained ferromagnetic materials, might be detected by an electromagnetic reading head.

Another object of the present invention is to provide means by which a row of symbols as set out above may be read into the circuits of a computer or other automatic device as a single binary number and, in the case where a data medium contains many such symbols arrayed in rows or columns, means are provided for selecting a single row or column from this array and reading it as a single binary number.

Still a further object of the present invention is to provide means for converting a binary number in the circuits of a computer or other automatic device into binary coded decimal or some other binary coded form.

The various objects set out above are accomplished primarily by adopting a numeral representation system as taught by the present invention. A data medium (format) is prepared so as to have a plurality of dot patterns established thereon wherein each dot pattern is substantially identical and includes three or more dots. By assigning values to given dot pairs of a given dot pattern, and weighting a given dot pattern with the assigned value when a line is drawn between that dot pair, it becomes possible to represent one of several numerals on a single dot pattern by drawing substantially straight lines between the appropriate dotpairs.

In addition to the particular convention described above thepresent invention teaches electronic systems for reading directly as binary numbers the numerals in the form suggested above. Primarily this includes generating trains of pulses which are directed sequentially to the space between the several dot pairs of a given dot pattern to determine whether or not a line has been drawn between those dots, and thus whether or not the particular dot pattern should be given the numerical weighting which is represented by that dot pair. An alternate form of the reading portion of the present invention includes a scanning system wherein a pulse is generated each time the scanning mechanism encounters a line between a dotpair, and by using control marks on the format together with the straight lines disposed between dot pairs, it is possible to give a proper weighting to the particular straight line giving rise to a pulse from the scanner.

The invention also teaches several specialized systems which highlight the functional capabilities of a system adopting the numerical form taught by the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 illustrate systems of numerals written in the dot pattern form of the present invention; FIG. 1 showing a three dot convention and FIG. 2 a four dot convention;

FIG. 3 is a block diagram of an electronic circuit for reading numerals written in the form of FIGS. 1 and 2;

FIG. 4 is an expanded block diagram of the portion of the system of FIG. 3 which directs pulses to the dot patterns on a data medium to interrogate specific dot pairs for connecting lines;

FIG. 5 is an expanded block diagram of the portion of the system of FIG. 3 which receives the information furnished by the pulses directed to a dot pattern and directs that information to an accumulation register means;

FIG. 6 is a block diagram of a system which enables the circuit of FIG. 4 to select which numeral in a row of numerals written in the form of the present invention that it will read;

FIG. 7 is a block diagram of a circuit which reads a row of numerals of the system taught by the present invention by scanning;

FIG. 8 illustrates possible scan paths which may be used in conjunction with the system of FIG. 7 wherein a four dot format is employed;

FIG. 9 is an illustration of scanning paths which may be used as alternates to the paths shown in FIG. 8;

FIG. 10 is a block diagram of a specific embodiment of a system for reading numerals in a four dot form by using the scan pattern of FIG. 8;

FIG. 1 l is a block diagram of a circuit which controls the particular row or column of numerals which are read from a large array of numerals;

FIG. 12 is a block diagram of a base counting circuit which is used in the several embodiments of the read portion of the present invention;

FIG. 13 is a block diagram of an alternate embodiment of a base counting circuit;

FIG. 14 illustrates simplified means for displaying numerals of the present invention;

FIG. 15 illustrates for purposes of comparison with FIG. 14 a number as it would appear if displayed by means of lights in register circuits associated with bi nary and binary coded decimal conventions;

FIG. 16 is a block diagram of a system which operates to convert a purebinary number into the form of a binary coded number; and

FIG. 17 is a semi-schematic illustration of a drum with numerical information of the present invention disposed thereon.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Numbers are usually written as a linear sequence of numerals a,,a,, a a a When a number is written in this way, the a are referred to as digits. When the Hindu-Arabic numerals are used, each a is one of the set of symbols 0,l,2,3,4,5,6,7,8, and 9. The value of a number written as such a sequence of digits is taken to be Hence if n pulses are counted into the register, then C(n) pulses are counted into it, the register will overflow.

Another unit which is employed extensively in forming a system for reading numerals of the present invention is referred to as a gate circuit, or simply a gate. A gate circuit has the properties that it transmits a received impulse if it also receives a bias from some other circuits; otherwise it will block the transmission of each impulse. In addition to the units described above, the present invention also makes use of pulsers (oscillators or free-running multivibrators) and delay circuits, both of which are well known in the art, and which in and of themselves form no portion of the novelty of the present invention.

One specific form of realizing the number system of FlG. 2, for example, so as to enable the numerals to be electronically read by a computer or the like, is to have the dots forming the pattern printed with an electrically conductive ink and the straight line segments drawn with electrically conducting ink or lead. FIG. 3 illustrates a system for reading numerals which are realized in this particular specific form.

Referring now to FIG. 3, a reading head 1 1 comprises a rigid sheet of nonconducting material 12 on which a set of metallic source pins 13 and a set of metallic detector pins 14 are mounted. The pins are distributed over the surface of the nonconducting sheet 12 in such a pattern that at least two pins one source pin 13 and one detector pin 14 make contact with the preprinted format along the locus of each possible line segment when the format is positioned correctly with respect to the reading head and when the reading head is pressed down upon the data medium.

In reading a numeral of N possible straight line segments, the read circuit employs a sequence of N pulses 16. The pulses l6 emanate from a pulse generator means 17 and are directed to a network of gate circuits 18 which directs one pulse (in a manner to be described in greater detail below) to one of the pins 13 at the locus of each of the various possible line segments which may be used to construct a numeral. If there happens to be a conducting mark connecting a pin 13 to a pin 14, the pulse will pass along that mark to the pins 14 and from there to a detector gate circuit network 19 which directs the pulse to one of several inputs 21 of an accumulator register means 22. If a pulse is passed to a pin 14 due to the presence of a line segment having the assigned value 1, then the detector gate circuit network 19 directs a pulse to the input of register means 22 leading to the first stage 220 thereof. In a similar manner a pulse to the detector gate circuit 19 due to the presence of a line segment having the value 2 results in the detector gate circuit network directing a pulse to the second'stage of the accumulator register means 22b; a pulse to the detector gate circuit network 19 by virtue of the presence of a line segment having the assigned value 4 is directed to the third stage of the accumulator 220; a pulse to the detector gate circuit 19 due to the presence of a line segment having the value 2" is directed to the nth stage of the accumulator 22n. Thus the accumulator 22 is in the register into which a number is read in binary form when the read circuit is in operation. 7

FIGS. 4 and illustrate a specific embodiment of a read circuit designed to read numerals written on four dot patterns, such as those of FIG. 2. The circular pins 1, 2,3 and 4 correspond to the pins 14 of FIG. 3 and make contact with the dots of the preprinted format which, as previously mentioned, are advantageously printed with ink having a high electrical conductivity. The rectangular pins 5, 6, 7 and 8 corresponding to pins 13 of FIG. 3 make contact with the marks, if any. drawn between dot pairs. FIG. 4 illustrates the portion of the read circuit hereinafter referred to as the source circuit, and FIG. 5 illustrates the portion of the read circuit hereinafter referred to as the detector circuit. The source circuit operates to direct pulses sequentially to each of the rectangular pins, while the detector circuit directs pulses which pass from a rectangular pin to a circular pin to the appropriate stage of the accumulator register means 22.

The source circuit (FIG. 4) comprises pulse generator means 17, the source gate circuit network 18 which includes four gate circuits A'E A'B, AB, and A8, a source gate circuit control circuit 24, which includes a delay circuit 26, and two flip-flop circuits Ali. and 8/3 The source circuit further includes a base counting cir cuit 27, which will be described in greater detail below, and a state register control gircug 28 including a series of flip-flop circuits C/G, D/D, E/E, etc. where the number of such circuits depends on the number of digits in the numbers which the circuit is designed to read. The detector circuit (FIG. 5) comprises the detector gate circuit network 19 which includes four gate circuits A'B, A'B, A-E andA'fi corresponding to the four gate circuits of the source circuit, and the accumulator register means 22.

The control circuit 24 controls both the gates of source gate circuit network 18 and the gates of detector gate circuit network 19 even though no connection is indicated between these components. The two states of the first stage of circuit 24 are designated by A and A. In state A, this stage blocks any pulse which is received, while in state A it transmits the pulse. The second stage either blocks or transmits a pulse depending on whether it is in its state B or Ii, respectively. It is the function of these two stages to control the functioning of the gate circuits in both the source and detector circuits by supplying them with appropriate biases. For example, if the first stage A is in state A it supplies a bias also designated by A to the gate circuits labeled AB and Ali; if it is in state A it supplies the bias A to the gates AB and K-Ii. A similar function i s performed by the second stage. The gate labeled AB passes only a pulse if it receives both the bias A and the bias E. The

labeling of the other gate circuits indicates analogous operation.

For the purposes of the present invention the nonconducting states of the stages of the accumulator register means 22 are taken to have the value zero, while the conducting states of the individual stages are taken to have the values one, two, four, eight, 16, etc. starting with the first stage in the series. When the numeral being read has a four dot pattern, and where neither intersecting nor diagonal lines are assigned numerical values, a sequence of four pulses from pulse generator means 17 is required to read one numeral. Just prior to the first pulse being issued from the. pulse generator means 17 (at the start of the read operation) the two stages of the control circuit 24 are in states A and B, respectively. Thus, the first pulse from generator 17 passes through source circuit gate A13 to rectangular pin 5. If a line is drawn between the dots which are con- Here b is called the base and b" is taken to mean b raised to the nth power. For instance, the number 5,432 (with the base l0 implied) has a value 510 410 310 2. For the sake of the discussion a will be termed the lowest ranking digit and a, the highest ranking digit. If b is 10, all the numerals 0 through 9, inclusive, may be used for the a and a number so written is called a decimal number. If b is eight, only the numerals 0 through 7, inclusive, may be used for the a,, and a number so written is called an octal number. If b is two, only the numerals zero and one may be used for the a,, and a number so written is called a binary number. Occasionally it is useful to express each of the a, as binary numbers even though a base such as 10, eight, etc. is being used. When expressed in such a way, a number is said to be in binary coded decimal, octal, etc. form.

This invention includes a new process for recording data in a form in which it may be easily read by electromechanical devices and, when read by such devices, the data may be fed into the circuits of a computer or other automatic devices in a form which may be used with no additional transcriptions. The process or method consists primarily of the two steps of recording the data in a new system of numerals on preprinted formats (data medium) and the use of one of several electromechanical devices described herein below to read numbers recorded in the new numerals into the circuits of a digital computer in the form of binary numbers.

- To record a multi-digit number in the system of the present invention, each digit is written in its binary representation. It is not, hwoever, written in the conventional binary form utilizing zeros and ones but is instead written in a special form and according to the following rules. Each numeral is written on a preprinted format consisting of N dots where N may be three, four, five, etc. depending on the purpose of the particular embodiment of the invention. The numeral is constructed by connecting dots with substantially straight line segments wherein, for most applications, only nonintersecting line segments will be used.

The line segments connecting the different pairs of dots of a given pattern are assigned to values one, two, four, eight, etc. in the read process. The number of dots, their spatial distribution and the assignment of values to the line segments which may connect them is not limited to the particular values suggested above, but in fact will be different in difi'erent embodiments to best suit the particular application to which the invention is being put.

Referring to FIG. 1, a specific example of numerals written in the system of the present invention includes a three dot format with lines connecting dot pairs assigned the values one, two and four starting with the line segment on the left side of the format and proceed ing clockwise. FIG. 2 illustrates a four dot format wherein the line segments are assigned the values one, two, four and eight starting with the line segment on the lower left side of the format and proceeding clockwise with the cross connections not being used. Once again it is to be emphasized that the particular assignment of values suggested above are not unique, and a different assignment of values would not transend the concept of the present invention. In the case of the three dot format of FIG. 1 there are three! (=3X2Xl 6) possible different assignments (combination of dot connecting line segments), and in the case of the four dot format there are four! possible different assignments. The number of assignments in the case of the four dot format can be further increased by the use of the cross connections which are not utilized in the convention adopted in FIG. 2. The particular assignment of values selected for the examples of FIGS. 1 and 2 were chosen primarily to make it easy to learn the numerical value of a given set of lines in a particular dot pattern. The four dot pattern has the characteristic of having the lowest number of dots giving rise to nine or more possible line segment combinations making this pattern suitable for representing a decimal digit convention.

The following description of the numeral reading systems of the present invention is in terms of basic, standardized, electronic units which are well known to the electronic art and are capable of being physically realized in several forms.

The units which will be referred to below include flipflop circuits which, as is well known, exist in only one of two possible states when in operation and upon receipt of an impulse flip into the other of its states. In one of its two states it not only response to an impulse by changing states, but also by transmitting the received impulse to any other circuit with which it happens to be associated; in its other state it blocks the transmission of the received impulse and merely changes state. In conforming with normal practices the "two states of the flip-flop circuits will be referred to as the conducting and nonconducting states. Another unit which is referred to below is a register, which comprises a number of flip-flop circuits connected in series so that each transmits its impulse to the next in the series. The particular flip-flop circuits comprising the register are referred to as the first, second, third, etc. stages of the register starting with the first circuit in the series. In many cases special provision is made to place every stage of the register in the same state by means of a single signal. This operation is referred to as resetting the register. In most cases a register is reset such that all of its stages are placed in their nonconducting state, but the present invention employs a resetting signal which is in fact an exception to this practice. In operation, if N pulses are transmitted into a register all of the stages of which were initially in their nonconducting states, then the state of the register may be taken to represent N in binary form with the conducting state of each stage representing the numeral one, the nonconducting state of each stage representing the numeral zero and with the first, second and up through the last stage standing for the lowest ranking, second ranking, and up through the highest ranking digit in the number, respectively.

In describing the present invention reference is made to the overflow of registers. If it is assumed that the exact number N of pulses have been transmitted into a register to cause all of the stages of the register to be in their conducting stage, the next pulse transmitted to the register will cause all of the stages thereof to go into their nonconducting states, and if the output of the final stage is connected to another circuit a pulse will be transmitted to that circuit and the register is said to have overflowed. Reference will also be made to the concept of the complement, C(n) of a number n in connection with some registers. Here C(n) is defined as C(n) N+ln for a register whose capacity is N.

tacted by pins 1 and 4, then the pulse will travel to pin 1 and from there through the detector circuit gate A-B into the first stage of the accumulator 22. The first pulse also passes through the delay circuit 26 to the control circuit 24 and flips the first flip-flop thereof from state A to state A When the state register flips from A to A the only source ch'cuit gate which can pass a pulse changes from A8 to AB, such that the second pulse from pulse generator means 17 interrogates the space between the dots contacted by pins 1 and 2, and if a mark is detected, a pulse is directed from pin through the gate A-B of the detector gate circuit network to the second stage of the accumulator register 22. The second pulse also passes to the delay circuit 26, after which it operates to change the first stage of the state register back to A, and the second stage to E.

Columns 1 and 2 of Table 1 below summarize the sequence of events described above, while columns 3 and 4 summarize the subsequent series of events in the read operation for the third and fourth pulses.

Several variations of the circuit arrangement of FIGS. 4 and 5 are possible and bear mentioning at this time. In one such variation the detector circuit gate circuit AB and AB may both be connected to pin 4, and the detector gates AB and AB may both be connected to pin 2. This is true since a pulse at pin 2 will be directed to the proper stage of the register by virtue of the control effected by the detector gate circuit network, such that the particular direction of travel of a pulse along a line connecting two dots is not a factor which is employed by the system. In another variation, detector gates A B and A B may both be; co nnected to pin 1 and the detector gates A B andA -B may TABLE 1 2| N mm M 1 WI A an meet a gate A-B and thence into the stage of the accumulator This pulse, after passing throu h the delay circuit fli s the control circuit from state into state lst 2nd 3rd 4 both be connected to pin 3. In any of these arrangements the connection of the source circuit to the pin set 5, 6, 7 and 8, and the connection of the detector circuit to the pin set 1, 2, 3 and 4 may be reversed. By thisit is meant that the pin connections of the gates A13, A13, KB and K-fi in the source and detector circuit may be interchanged, provided they are all interchanged. Either reconnection of the source gates to the next higher numbered pin in the set 5, 6, 7 and 8, or reconnection of the detector gates to the next lower number pin in the set 1, 2, 3 and 4, is possible. If one of the pins, say 4 for example, is divided into two separate parts 4a and 4b, and the corresponding dot on the preprinted format is divided into two separate parts, then only the pir 1 set 1, 2, .3 and 4 is necessary. The source gates A-B, A-B, A'li and "A -B may be connected to pins 4a l, 2, a nd 3, respectively, and the detector gates A-B, A-B, AB and Afi may be connected to pins 1, 2, 3 and 4b, respectively. In this arrangement care must be taken that pins 4a and 4b are never connected electrically. It should also be mentioned that the set of four gate circuits in the source circuit, each olf which is controlled by two biases, might be replaced by a set of six gate circuits, each of which is controlled by a single bias. These six gates would be arranged in a tree-like circuit with the output of the pulser going to both of two gates which are opened by the biases A and A, respectively. The output of each of these gates would go to both the pair of gates opened by the biases B and respectively.

A multi-digit number can be written on a preprinted format with the individual digits of such a number represented by numerals of the present invention. In such a case, the reading head 11 has a separate and identical set of pins 13 and 14 for each numeral. The transmission of pulses from the source circuit to the pins in the reading head, or from the pins to the detector circuit are controlled by a set of gate circuits which allows only one numeral in the row of numerals constituting the number to be read at a time. if a number is written as a row of numerals a, a,, a a a to the base b as described above, the read circuit will read a into the accumulator one time, a, into the accumulator 12 times, a, into the accumulator b times, a into the accumulator 12 times, a,, into the accumulator b times, etc. The biases that control which numeral in a row of such numerals is being read are provided by the control circuit 28 which receives pulses from the base counting circuit 27 and supplies the appropriate biases to the gate network 18 so that pulses are transmitted only to the pin set making contact with that particular numeral. Alternatively, the control circuit supplies appropriate biases to the gate network 19 so that pulses are transmitted to the accumulator only from the pin set making (contact with that particular. numeral. In addi tion, the'control circuit 28also operates to provide bias to the base counting circuit 27. i

For the case where numerals are constructed from N straight line segments, the base counting circuitreceives one pulse from the state register portion of circuit 24 for each N pulses emitted by the pulser. This follows since the last stage of the state register changes state and transmits a pulse only after N pulses have been received by the circuit from the pulse generator means 17. Accordingly, the base counting circuit 27 transmits one pulse to the circuit 28 for each 1, b, b, b, b pulses that it receives. The biases that the base counting circuit receives from the circuit 28 determines how many pulses must be received by it before it transmits a pulse.

Assuming the parameters used above, if a is being read, the base counting circuit transmits a pulse when the pulser has emitted one set of N pulses; if a, is being read, the base counting circuit transmits a pulse when b sets of N pulses have been emitted by the pulse generator means; if a, is being read, the base counting circuit transmits a pulse when b sets of N pulses have been emitted by the pulse generator means; if a, is being read the base counting circuit transmits a pulse when b" sets of N pulses have been emitted; etc. Since the circuit 28 operates to control which particular digit is being read, and it changes the reading device from one digit to another each time it receives a pulse, each pulse emitted by the base counting circuit causes the read device to read a different digit, and causes a digit to be read a number of times corresponding to its base value b".

FIG. 6 illustrates a circuit arrangement which obviates the necessity of having a separate source gate circuit network 18, or detector gate circuit network 19 for each numeral forming a portion of one number to be read by the present invention. In other words, for the system described above, it would be necessary in order to read a six digit number for six separate source gate circuit networks or detector gate circuit networks to be provided. Since it may be desirable to have a capability of reading numbers with a relatively large number of digits, the circuitry could become so complex and unwieldy as to render the system impractical. FIG. 6 illustrates a portion of a reading circuit which has the capability of reading a multi-digit numeral, and, at the same time, requires only a single source gate circuit network and a single detector gate circuit network. The necessary selectivity is provided by a series of gates C'D-E, -12, 05-5, GDE, C'D-E which are controlled by control circuit 28 and which are interposed between either network 18 or 19 and the pin operatively associated with those networks. The condition of the flip-flop circuits forming circuit 28 determines which one of the several pin sets have access to the rest of the read system, and each pulse from the base counting circuit to the circuit 28 operates to change the condition of the flip-flops forming circuit 28 such that a different one of the pin sets is operatively engaged with the remainder of the read circuit. The flip-flops of circuit 28 operate not only to select a particular digit for reading, but also, as previously mentioned, operate to provide bias to the base counting circuit whereby the particular digit selected for reading is counted into the accumulator a number of times corresponding to the appropriate base value of that digit. It is this consideration which determines which condition of the flip-flops of the circuit 28 are associated with which digits. Thus, by having gate C-D'E associated with the digit having a base value of 1 (assuming a decimal number system) and having the system initially start with all of the flip-flops of the circuit 28 in their nonconducting state, it becomes clear that the digit shown to the extreme right in FIG. 6 is the only digit communicating with the gate of either circuit 18 or 19, and thus the only digit operatively associated with the read circuit. After N pulses have been issued from the pulse generator means 17 the base counting circuit receives a pulse and transmits it to the control circuit 28, (the bias to the base counting circuit when all of the flip-flops of the state register are in their nonconducting state being such that a pulse received by the base counting circuit is transmitted) whereby the first stage of the circuit is changed to its conducting state wherein the digit having a base value is placed into operative connection with the read circuit in place of the digit having the base value 1. When the first stage of the control circuit 28 is in its conducting state and 'all of the remaining stages are in their nonconducting digit having the base value 10 will be read into the accumulator ten times, and thus given its proper base value along with its particular numerical weighting. Particular circuits for performing the function of the base counting circuit in response to the biasing of the control circuit 28 and pulses from the read control circuit will be set forth in detail below. The present invention is, of course, not limited to a decimal numerical structure, as will be clear to those having a familiarity with the basic circuits employed in the present invention. A summary of the operation of a circuit conforming generally to the configuration as shown in FIGS. 4, 5 and 6 is summarized in Table 2 below.

The form of the present invention described above wherein each digit on a format is separately engaged by a separate set of reading pins, is particularly useful in connection with processing numerical information, such as that found on bank drafts (checks), utility company receipts, retail merchant sales documents, etc., all of which are characterized by a relatively small number of digits which must be processed per document in order to obtain all of the desired information from such TABLE 2 The base counting circuit, a it is used in this invention, will transmit the lst th IOOOOth pulse from a sequence of pulses received by it when the CDE flip-flops are in states respectively.

Hence the pulse to pass through both fli flops, AIA and B CDE flip'tlops from I,000th 55E col 5 l,000th 10,000th (:51; wow

C'DE Ist or '85? 86! ID allow a lst digit in the number to be read in times 2nd 3rd 4th 5th above requires gate circuit means to transfer the reading functions from one digit to another such that, if a large number of digits are simultaneously involved, the necessary gating circuitry becomes uneconomically large and complex.

Thus, referring to FIG. 7 the present invention teaches a system for reading numerals of the present invention which scans whole rows of numerals, such as numeral 41, with a set of sensing devices 42 and 43. While the particular embodiment of FIG. 7 illustrates two separate sensing devices for scanning the numerals 41, it is within the scope of the present invention to construct a scanning mechanism having a single sensing device; the important feature of the scanning mechanism does not reside in the number of sensing devices employed, but rather that in scanning a numeral each space between dot pairs wherein a line segment assigned a numerical value can be drawn, is crossed, and thus interrogated by the scanning mechanism. In the same way that thenumber of sensing devices and the paths which they may follow will necessarily take varied forms to most efficiently fulfill the specific requirements of a particular application, the nature of the sensing devices themselves is also subject to a relatively wide variation depending primarily on the electronically detectable characteristic of the substance used to define the format dot patterns and the lines drawn be tween dot pairs thereof. One particular means for scanning includes the use of photocells. A lens 44 focuses light from a very small spot on the surface of the paper (a light being reflected from a light source not shown) through an aperture leading to a photocell 46. The electro-motive force of the photocell will be relatively constant as long as the scan spot does not cross a mark of any kind. When the scan spot crosses ,a mark, however, the electro-motive force of the photocell will make a sharp and distinct dip if the width of the mark is about the same size, or larger, than the diameter of the scan spot. Another possible method of scanning involves the use of ink or lead containing materials of high magnetic permeability. As the paper containing the numerals passes between the poles of a sensitive electromagnet. the marks are carried between the poles of the magnet causing a small change in reluctance in the magnetic circuit. This change in reluctance in turn produces a small variation in the current through the windings oi the electromagnet. As mentioned above, however, the precise method of sensing the marks is not a part of the present invention and the techniques mentioned in this paragraph are only presented as examples to make it clear that there are several means for sensing marks presently well known in the art which could he successfully employed for use with the present invention.

Since it is possible that the output of any sensing device may be too weak by itself to operate an accompanying circuit, it would be reasonableto expect amplifiers to be used in conjunction with such sensing devices. The amplifier would then transmit its output to a circuit known as a voltage gate, the function of which is to filter out the smaller variations in voltage and to transmit the larger ones to a circuit performing the function of a pulse shaper. The pulse shaper operates to produce a pulse of uniform magnitude and duration each time a voltage variation is experienced which is of sufficient magnitude to get past the voltagegate. The circuits performing these functions are represented by the blocks 47 in FIG. 7. In order for the reading system of this embodiment to raise the various digits of the format to their appropriate base level, it is necessary to provide a row of control marks 48 on the format. A separate scanning mechanism 49, including a sensing means 51 and appropriate circuit means 52, is provided for scanning the control marks. The output of the scanning means 49 is directed to a control circuit 53 which provides the biases which control the read operation. The number of control marks 48 and the movement of the scanning means 49 relative to the scanning means 42 and 43 is such that N marks 48 are scanned during the time the scanners 42 and 43 scan a single digit 41 wherein the digit 4]. includes N possible straight line segments between dot pairs of the dot pattern which have been assigned numerical values. Hence, the sens ing device 51 emits N pulses during the scanning of each numeral position, making it possible for the control circuit 53 to provide N bias patterns as required.

When either of the scanning means 42 or 43 detects a line it emits a pulse which is directed to a pulse generator means 54. A pulse from the scanning mechanism to the pulse generator means 54 operates to activate the pulse generator, wherein pulses are directed from the pulse generator means to a gate circuit network 56 and a base counting circuit 57. The gate circuit 56 is electrically disposed between the pulse generator means 54 and an accumulator register means 58 which has a plurality of inputs 59 equal in number to the number of difierent line segments which are assigned numerical values. The gate circuit network 56 operates in essentially the same manner as the detector gate circuit network 19 of FIG. 3 in that it directs the pulses which it receives into the nth stage of the register when the numeral line having the value 2" is sensed.

In the scanning of a multi-digit number the scanning device may scan from the highest valued numeral a, to the lowest a or from a to a,,. The control circuit 53 also controls the operation of the base counting circuit 57, which in turn determines the number of pulses emitted by the pulse generating means 54 when a numeral mark is detected. This control consists of shutting off the pulser after one pulse has been emitted when a mark is detected in a or after b pulses have been emitted when a mark is detected in a,, or after I: pulses have been emitted when a mark is detected in a,, or after b pulses have been emitted when a mark is detected in a,,. To perform this operation, the control circuit counts each set of N pulses produced by the control sensing unit 51 and provides a unique and different bias for the base counting circuit 57 for each set of such pulses.

For the purposes of illustrating the operation of a scanning system in reading a number, it is assumed that numerals are written on a format in four dot patterns according to the convention of FIG. 2. Two scan patterns along which sensing devices could move in their scanning patterns are shown in FIGS. 8 and 9. In traversing these scan patterns, either the medium on which the numerals are written or the sensing devices could be moved. FIG. 10 illustrates a circuit designed for operation along the paths shown in FIG. 8 wherein scanning means U, and U, are employed for reading the numerals while a scanning means U, scans the con trol marks. As U, and U, scan each numeral, U scans a series of four control marks along the edge of the medium on which the numerals are written. The pulses produced by the control marks are directed into a control circuit 61. In this particular system a base counting cirguit 62 is not interposed between the control stages 13/8 and C/C as suggested in embodiments described above, but is used in the read circuit to turn off a pulse generator means 63 after an appropriate number of pulses have been transmitted to an accumulator register means 64. As best seen with reference to FIG. 8 the sensing devices U, and U, move in straight, parallel paths with sensing device U, leading device U, by a length which is approximately one-quarter of the width of the numeral dot pattern. The first operation in the reading of a numeral occurs when U, crosses the position of the mark in the fours position in the numeral (see FIG. 2). The resulting signal from U, starts the pulse generator means 63. The pulse generator means emits pulses until a pulse gets through the base counting circuit and back to the pulse generator means to turn the generator means off. The number of pulses which the pulse generator means has to emit before a pulse is able to get through the base counting circuit to shut off the pulse generator means is controlled by the base counting circuit 62, which is in turn controlled by the bias provided from control circuit 61. At th i s initial stage in the operation, the stages AIA and B/B are in state A-B. Hence the pulses from the pulser (if any) all go through gate A-B disposed between the pulse generator means 63 and the register accumulator means 64. Hence the pulses from the pulser go through gate A-B into the fours (3rd) stage of the accumulator 64. At this point the control sensor U crosses a control mark and transmits a pulse into the control circuit 61 (state register) which flips the state register into state AB. The sensing device U now crosses the line in the eights position in the numeral. The output of the pulser, if any, now goes into the eights (4th) stage of the accumulator. These operations and subsequent operations in the reading of a numeral with the scan system illustrated in FIG. are summarized in Table 3 below. The A and B designations between control marks shown in FIG. 8 indicate the states of the flip-flop circuits before and after a control mark is passed by the sensor U,.

The circuit of FIG. 10 can, with very minor modification, be used for the scan pattern of FIG. 9 wherein a single sensor U is employed in the place of the two sensors of FIG. 10. The syste m need only be modified by reconnecting the gate A'B to stage 1 and gate A13 to stage 2 of the accumulator 64 and eliminating one of the two sensing devices. The pattern of control marks needs also to be changed, whereby the sensing device U, follows a path similar to the path of the sensing device U TABLE 3 Sensing unit I 1 2 l 2 crosses the position of the mark in the position in the numeral. The pulse from this sensing unit starts the pulser and transmits pulses to the gate and base counting circuits. Since the stages AIA and B/F of the control circuit 61 are in state these pulses go into the stage of the accumulator.

U, now transmits another pulse into the control circuit which flips it into state 3rd 4th 2nd Occasions may arise when it is desired that a number of the form a a a a a, be read into an accumulator register in its correct binary fon'n. As indicated by the notation, the lowest ranking digit a in this number is not the coefficient of one (b=l) as previously specified but is the coefficient of b, where i is greater than or equal to I. For instance a quantity may be measured as having a magnitude of 283,000 with an accurancy that allows the first three digits to be specifled but not the last three. Hence this number could be recorded as 283 X 10. Furthermore, it might be desired to record this number in a space on a preprinted format in which there was not enough room for all six digits. If the accumulator is nevertheless large enough to accommodate a number of this magnitude in pure binary form, it would be desirable to be able to read such a number without the necessity of recording all six digits.

The present invention teaches a provision for carrying out the desired operation outlined above, as will now be fully explained. The exponent i of the base b associated with the lowest ranking digit a, can be recorded in a special numeral position which is read by the read circuit prior to reading the rest of the digits. Provision is made in the circuit to read i directly into the control circuit 28 (see FIGS. 3 and 4) in the case of the conduction read system. In the case of a scan system, i is read directly into that part of the control circuit 61 (see FIG. 10) which controls the base counting circuit, namely the stages labeled C/C, D/fi, E/E, etc. The reading of the numeral then starts with the reading of the lowest ranking digit 4,. Each mark in a, results in b pulses being counted into the appropriate stage of the accumulator register. The reading of the rest of the number proceeds as described previously with the exponent of the base b being increased by one for each successive digit.

The exponent i may be distinguished from the number digits on the preprinted format by being placed in a field on the format reserved for this purpose. The gate circuit network 18 (see FIG. 3) directs the pulses to the source pin set making contact with this numeral first. The corresponding detector pin set would be connected to a special gate circuit network similar to gate circuit network 19 but controlled only by the contro circuit 24 which would direct the pulses to the control circuit 28 rather than to the accumulator. In the case of the scan system, the exponent i would be scanned by the same sensing units used to scan the other numerals and the resulting pulses directed by the gate circuit network 60 (see FIG. 10) into the appropriate stages of the control circuit 61 or it could be scanned by a special sensing unit whose operation would be controlled only by the stages 61 corresponding to those labeled Ali and Blfi.

It is intended that the circuitshown in FIG. 10 be used in conjunction with other electro-mechanical devices which will enable this circuit to read selected numbers from an array of such numbers written in a coded form such as that of FIGS. 1 or 2 in rows and columns on a data medium such as a sheet of paper. It is a part of the function of the electro-mechanical devices to provide a capability for the periodic scanning of such an array of numbers by a set of sensing elements. Referring to FIG. 17, the paper .71 on which the numerals are written may be mounted on the outer surface of a drum 72 which may be rotated rapidly. Here we will adopt the convention of rows and columns in such an array that a sequence of digits representing a single number is written in a row and the columns of numerals or numbers are perpendicular to the rows. The rows of numerals may be either parallel to the axis of the drum or run circumferentially around the drum in different embodiments. As the drum rotates, pairs of sensing devices 73 having scanners U, and U, and mounted on a rigid bar 74 close to the external surface of the drum scan the format positions in each circumferential row or column as they pass. In order to select the row or column to be read, only the sensing devices scanning that row or column are activated. For an embodiment using photocells as sensing devices, duplication of the read circuits may be avoided by use of optical fibers in the following way. Optical fibers run from the U scan paths in each row or column to a single photo-cell U and similar optical fibers run from the U scan paths in each row or column to another photo-cell U Selection of the circumferential row or column to be read is accomplished by illuminating selectively only that row or column.

For the case where the rows of numbers run circumferentially around the drum, and the columns run parallel to the axis of the drum, provision will be made to read the numbers in a particular column by the use of a row of control marks 76 along the edge of the paper and running circumferentially around the drum. Referring to FIG. 11 as well, as the drum rotates these marks are scanned by a sensing device U,, which delivers its count into a register 77, called the control register, which is just a series of flip-flop circuits connected in series. Each mark 76 in the control sequence is placed so that it is sensed just before U, and U, arrive at the position of the number to be read and after they have passed the position of the previous number in the row. The next mark in the control sequence is placed so that it is sensed just after U, and U pass the position of the number that has been read and before they arrive at the position of the next number. The control marks in this sequence are called the column marks. When a number in column n is to be read, a control circuit 78 or the operator counts C(n) pulses into the control register 77. Here C(n) is the complement of n. The last stage in the register 77 transmits its pulses to the light switching circuit 79, off/on, and to a control flip-flop circuit H/Il. When the register 77 has had N pulses counted into it, all of its stages are in their conducting states. Hence, the next pulse clears it, flips the light switching circuit off/on from off to on, and flips H/H from H to H. The next pulse after this one puts a count i n the register 77, and passes a pulse through a gate H operatively disposed between control circuit 78 and both circuit H/H and switch 79, which flips circuit H/H from H into H and flips light switching circuit 79 from on back to off. Whether or not there are N+1 columns of numbers, the row of control marks 76 controlling this operation has N-l-l marks in it somewhere. Hence, if no number is placed in the register 77, the read circuit will only be in operation after it passes the last mark on the page and before it reaches the first mark again. If a number C(n) is in the register 77 it will count n marks, read until it finds the next mark, then count N+l marks (or go one complete revolution) before it reads again. Hence, unless further control is provided this device will read the number it is set to read once each revolution. To further control the read operation, come device (not shown) is used to emit a pulse or signal once each revolution when the read device is passing the last mark in the control sequence. This pulse or signal will be called the turn signal. Further control circuits may count these pulses to control how many times a particular number should be read by the device.

In the event that the rows of numerals run parallel to the axis of the drum, and the columns of numbers run circumferentially around the drum, the scan paths will pass vertically through the numerals instead of horizontally as shown in FIG. 8. In this event the gate circuits shown in FIG. ll) would have to be reconnectedtothe appropriate accumulator stages to conform to the sequence in which U and U cross the marks in the dif ferent positions in the numerals. The state regi ster i s rearranged so that the flip-flop circuits, C/C, D/D, E/E, etc., no longer receive pulses from the flip-flop B/fi but are used to count the turn signals. The sequence of control marks, which was used above to identify columns in which a number was to be read, is now used to identify the row. Hence the marks that were called the column marks in the paragraph above will be called the row marks. Hence one numeral in: a given number will be read during each revolution of the drum. The bias from the flip-flops CDE control the base counting circuit as has been described previously. The application of the voltage from the light switching circuit to the various lights illuminating the different columns of numerals is controlled by the CDE biases by means of gates in a manner shown in FIG. 16. Thus in the reading of a multi-digit numeral the first numeral on the right is read in on the first revolution of the drum with one pulse for each line crossing, the second numeral from the right is read in on the second revolution with 10 pulses for each line crossing, etc.

The control marks in FIG. 7 could be used for either the column or row marks. For numbers constructed of N line segments (and, hence, using N control marks for the reading of each numeral), the control circuit 78 could transmit every N control mark pulse into the control register 77 as a row signal when the rows of numerals run perpendicular to the scan paths. When the rows of numerals are parallel to the scan paths and when each number is written on an m digit fonnat, the control circuit could transmit each (m-N)" control mark pulse to the control register 77 as a column signal.

Table 4 sets forth how the base counting circuit processes a sequence of digits. If a number is to be processed (read, etc.) starting with the lowest ranking digit then N,,N,,N,,N etc. are l, b,b,b ,b, etc., where b is the base. If the number contains six digits, and it is to be processed starting with the highest ranking digit then N,,N,,N ,N ,N and N,, are lr'flbflbfibfib, and 1, respectively.

Referring to FIG. 12, the portion of a base counting circuit which blocks or transmits the pulses which it receives are the set of gate circuits G, which are connected in series. Each of these gate circuits will transmit a pulse if it receives a bias from each of two other associated circuits or if it receives no bias at all. If it receives a bias from only one associated circuit it will block the transmission of a pulse. One of the circuits which provides biases for the gates is the series of flipflop circuits 81 referred to as thebase register. The number of flip-flop circuits in this register is equal to the number of gate circuits G. Each flip-flop in the series 81 provides a bias to its corresponding gate G when it is in its conducting state but provides no bias if it is in its nonconducting state. The second bias is provided to some of the gate circuits by a set of circuits which are controlled by a control circuit such as circuit 61 of FIG. 10. The circuits which provide these biases are designated GB, GD, CT), and 6 5*, respectively. These labels are intended to signify that these circuits provide biases to their associated gate circuits G when the control circuit is in the state designated by the label. For the sake of brevity, the base counting circuit in FIG. 12 is designed to control the processing of numbers containing 7 only four digits. Hence, only two flip-flops in the state regis- TABLE 4 N l N l N l N l N l N 2M Natl N518 Null l pulse depending on whether the control circuit is in state etc.,

respectively,

' C'D-E 'C D E ter, CK: and D/5, need be used to provide biases for this operation. In a base counting circuit intended for processing numbers with more than four digits, the bias circuits would be controlled by the flip-flops E/E, etc., in the control circuit also. The circuit shown in FIG. 12 is also set up to read numbers written to the base 10 starting with the lowest ranking. Table sets forth the operation of this circuit. The sequence of pulses which is being transmitted to the base register is also being transmitted after a slight delay caused by a delay circuit 82, to the series of gates G. The particular pulses which cause the biases received from the bias circuits CD to be exactly matched by the biases received from the base register 81 are thus the only pulses in the sequence which are able to pass through all the gates G. Each of these pulses resets the base register and performs all the operations ascribed elsewhere in this description to the base counting circuit.

FIG. 13 shows in block diagram form another base counting circuit. This circuit is again only capable of processing four-digit numbers. However, to show how the base counting circuit may be used to process numbers starting with the highest ranking digit, the bias circuits of FIG. 12 have been rearranged. The flip-flop circuit in the base register 83 in this circuit differs in two ways from the flip-flop circuits in other registers in this invention. The reset function shown as a block 84 represents a circuit which resets the flip-flop circuits in the base register into the conducting state rather than into the nonconducting state as is usual, and the biases function to place and hold the flip-flop circuit to which they are applied in the nonconducting state regardless of the action of the reset circuit. The biases are only on during the reset op- TABLE 5 eration. Table 6 explains the operation of this circuit.

Referring to FIG. 14, the display of a single numeral stored in a register such as the accumulator can be accomplished by means of a sheet of opaque material 91 with slots 92 cut in it. These slots are arranged in a geometrical configuration identical to that of the new numerals such as that shown in FIGS. 1 and 2. A light 93 is incorporated in the appropriate part of each flip-flop circuit of the register containing the number represented by the numeral so that it will be lighted when that flip-flop is in the conducting state and be out when the flip-flop is in its nonconducting state. Such an arrangement is frequently used in binary scalar counting circuits of such devices as electronic counting equipment (Geiger counters, etc.) The lights 93 are placed behind the sheet of opaque material so that each light illuminates the appropriate slot. The lights with the values 1, 2, 4, and 8 are in the first, second, third, and fourth stages of the register, respectively.

To be displayed in the manner described above, a multi-digit number must be stored in a binary coded form in the circuits of the computer or other automatic device, i.e., each a, must be stored in binary form in a separate register or in a separate part of one register. In most digital computers or other devices using numbers in binary form, numbers are stored in pure vinary form. FIG. 15(a) shows how the number 5432 would appear in pure binary form; FIG. 15(b) shows how it would appear in binary coded decimal. Virtually all digital computers in use today have, among their output circuits, circuits capable of translating numbers from their pure TABLE 6 binary form to binary coded form. A circuit capable of perfomring this function is now presented as a part of this invention.

FIG. 16 is a block diagram of a circuit capable of converting pure binary numbers into a binary coded form. For the sake of brevity this circuit has been restricted to a size that can process only four-digit numbers. The design of devices to process larger numbers could be rnade by merely adding more flip-flop circuits, gates, etc. to the above circuit. This device consists of two registers, and 131, a flip-flop circuit F/F and a gate F which transmits pulses only when the flip-flop F/F is in the state F, four registers 134, 135, 136 and 137 and the gate circuits CD, 61), c5 and (3-5, which control the flow of pulses to the registers 134, 135, 136 and 137, respectively. It also utilizes a pulser 138, a base counting circuit 139, and a control circuit 140, all of the same kind described in other parts of this description. The boxes labeled external control circuit 141 represent the computer or operator that is utilizing this device.

In operation, this device takes a pure binary number whose value is x where and computes the coefficients a a a and a which it stores in binary form in the registers 134, 135, 136 and 137. To initiate this operation, the external control circuit 141 first transmits the complement of x, C(x), into the register 130, then starts the pulser 138. The c ontrol circuit 140 is in state CD and the flip-flop F/F is in state F. The pulser begins to transmit pulses simultaneously into the registers 130 and 131 and into the base counting circuit 139. In this application the base counting circuit must be set to process the digits starting with the highest ranking first as described with reference to FIG. 13. The subsequent sequence of operations is described below in Table 7. T he pulse which flips the con trol circuit 140 from CD to CD leaves the flip-flop F/F into state F so provision is made that this pulse flip F/F back into state F after it passes through the state register. In describing the above operation, explicit provision is made in FIG. 16 to reset the base counting circuit only when the register 130 overflows. The base counting circuit 139 also resets itself automatically when it transmits a pulse.

TABLE 7 Each time the pulser 138 transmits Ir b b 1 pulses to the base counting circuit 139, the base counting circuit transmits one pulse into register 134 135 136 137 because the state register is in state CD CD CD CD it also resets I31. After a a a, a, a, pulses have been transmitted into the register 134 135 I36 137 the number of pulses necessary to make I30 overflow is less than b b b 1 Hence I30 overflows and transmits a pulse. This pulse flips the control circuit from state CD CD CD 65 into state c-o c-i5 C c-o resets the base countin circuit, and

flips F from F to F.

The gate F now blocks pulses from gettin into the base count it circuit. The

remain er M- rF- r 'm xrwl ha IF. 0 is now stored in 13!.

The pulser now transmits C(n) C(x,) C(x,) pulses into both 130 and l3l. This causes into F. The process is now repeated until all digits are stored.

What is claimed is:

l. A pulse counting circuit comprising:

a. an accumulation register consisting of a plurality of flip-flop circuits connected in a series, each of said flip-flop circuits having a bias input operable to receive bias signals and each of said flip-flop circuits disposed to receive reset signals, wherein each said flip-flop circuit can exist in only one of two states, 0 and 1, and wherein each said flip-flop circuit is operable to be put in state 0 upon receipt of both a bias signal and a reset signal but is operable to be put in state 1 upon receipt of a reset signal only;

b. reset means operatively associated with each flipflop circuit in said accumulation register, said reset means disposed to receive pulses from the last flipflop circuit in said series, said reset means operative upon receipt of a pulse from said accumulation register to transmit a reset signal to every flip-flop circuit and bias signals to certain selected flip-flop circuits, whereby said pulse counting circuit is operative to transmit one pulse out of a number of pulses transmitted to it, said number being determined by the pattern of flip-flop circuits receiving bias signals.

2. In a numerical calculating device, the combination comprising:

a. a first accumulation register, said first accumulation register operable to count and record the number x of pulses received by it if said number x is less than the capacity N of said register, said first accumulation register further operable to emit a pulse and record x 0 if the actual value of it exceeds the capacity N of said register by l,

b. a pulser disposed to emit pulses into the first accumulation register, said pulser operative to start emitting a timed sequence of pulses upon receipt of a start signal and to terminate said sequence of pulses upon receipt of a stop signal;

. a counting circuit disposed to receive pulses from said pulser, said counting circuit operable to count the number x of pulses from a timed sequence of such pulses received by it from said pulser, said counting circuit further operable to emit a count pulse when said number achieves some desired value y, said counting circuit thereafter operable to start said pulse count from 0; and

d. a control circuit disposed to receive pulses from said first accumulation register, said control circuit operable upon receipt of a pulse to terminate transmission of pulses from said pulser to said counting circuit, whereby the sequence of operations started by a start signal to said pulser when a count of N+l-n is recorded insaid first: accumulation register results in a number k of count pulses being emitted by said count circuit where n y'k-i-r and where the remainder r is less than y. l

3. The device of claim 2 further comprising:

input means operatively associated with said first accumulation register and said. pulser, said input means operable to transmit a number c(n) of pulses into said first accumulation register, where c(n) N+l-n, and thereafter to transmit a start signal to said pulser.

4. The device of claim 3 further comprising:

a storage register disposed to receive and record said count pulses from said count circuits, whereby the sequence of operations starting with the transmission of c(n) pulses to the first accumulation register by the input means results in a count k in said storage register.

5. The device of claim 4 further comprising:

a. a gate circuit operatively associated with said con trol circuit, said gate circuit disposed to control the flow of pulses from the pulser to the counting circuit and operable to block or transmit said pulses in response to signals from said. control circuit; and

b. a second accumulation register substantially the same in operation and capacity as said first accumulation register, said second accumulation register further operable to be set to count upon receipt of a reset signal, said second accumulation register disposed to receive pulses from said pulser, to receive reset signals in the form of count pulses from said counting circuit, and to emit pulses to said control circuit whereby the sequence of operations starting from the transmission of c(n) pulses into said first accumulation register results in a count of k in said storage register and a count of r in said second accumulation register.

6. The device of claim wherein said gate circuit is operable to transmit signals from the pulser to the counting circuit if it receives a bias signal F but to block the transmission of said signals if it receives a bias signal F and wherein the control circuit includes:

bias means operatively associated with said gate circuit, said bias means consisting of a flip-flop circuit disposed to receive pulses from both the first and second accumulation registers, wherein said flipflop circuit can be in only one of two states, F and F, and wherein said bias means is operative to transmit a bias, F or F, to said gate circuit, whereby the sequence of operations starting from the transmission of c(n) pulses into said first accumulation register, said bias means being initially in state F, results in a count of k in said storage register and a count of c(r) in said first accumulation register where c(r) N+lr.

7. The device of claim 6 wherein said storage register includes:

a plurality of subregisters, each of said subregisters operable to count and record a number k of pulses received by it;

a gate network operatively associated with said control circuit and disposed to receive count pulses from said count circuit and direct said count pulses into one selected subregister.

8. The device of claim 7 wherein the control circuit further includes:

digit selection means operatively associated with said 9. The device of claim 8 wherein the control circuit further includes:

program means operatively associated'with said digit selection means, said program means operable to cause said digit selection means to assign successively values of b" to y, where b and m are integers and the exponent m progresses consecutively from a value M to the value 0, where b" is less than N, the capacity of the accumulation register, and where y is the number of pulses which will cause said counting circuit to emit a count pulse, said program means further operable to cause the successive values of k generated to be recorded in successive subregisters, said program means further operable to transmit a delayed stop signal to said 

1. A pulse counting circuit comprising: a. an accumulation register consisting of a plUrality of flipflop circuits connected in a series, each of said flip-flop circuits having a bias input operable to receive bias signals and each of said flip-flop circuits disposed to receive reset signals, wherein each said flip-flop circuit can exist in only one of two states, 0 and 1, and wherein each said flip-flop circuit is operable to be put in state 0 upon receipt of both a bias signal and a reset signal but is operable to be put in state 1 upon receipt of a reset signal only; b. reset means operatively associated with each flip-flop circuit in said accumulation register, said reset means disposed to receive pulses from the last flip-flop circuit in said series, said reset means operative upon receipt of a pulse from said accumulation register to transmit a reset signal to every flip-flop circuit and bias signals to certain selected flip-flop circuits, whereby said pulse counting circuit is operative to transmit one pulse out of a number of pulses transmitted to it, said number being determined by the pattern of flip-flop circuits receiving bias signals.
 2. In a numerical calculating device, the combination comprising: a. a first accumulation register, said first accumulation register operable to count and record the number x of pulses received by it if said number x is less than the capacity N of said register, said first accumulation register further operable to emit a pulse and record x 0 if the actual value of x exceeds the capacity N of said register by 1, b. a pulser disposed to emit pulses into the first accumulation register, said pulser operative to start emitting a timed sequence of pulses upon receipt of a start signal and to terminate said sequence of pulses upon receipt of a stop signal; c. a counting circuit disposed to receive pulses from said pulser, said counting circuit operable to count the number x of pulses from a timed sequence of such pulses received by it from said pulser, said counting circuit further operable to emit a count pulse when said number x achieves some desired value y, said counting circuit thereafter operable to start said pulse count from 0; and d. a control circuit disposed to receive pulses from said first accumulation register, said control circuit operable upon receipt of a pulse to terminate transmission of pulses from said pulser to said counting circuit, whereby the sequence of operations started by a start signal to said pulser when a count of N+1-n is recorded in said first accumulation register results in a number k of count pulses being emitted by said count circuit where n y.k+r and where the remainder r is less than y.
 3. The device of claim 2 further comprising: input means operatively associated with said first accumulation register and said pulser, said input means operable to transmit a number c(n) of pulses into said first accumulation register, where c(n) N+1-n, and thereafter to transmit a start signal to said pulser.
 4. The device of claim 3 further comprising: a storage register disposed to receive and record said count pulses from said count circuits, whereby the sequence of operations starting with the transmission of c(n) pulses to the first accumulation register by the input means results in a count k in said storage register.
 5. The device of claim 4 further comprising: a. a gate circuit operatively associated with said control circuit, said gate circuit disposed to control the flow of pulses from the pulser to the counting circuit and operable to block or transmit said pulses in response to signals from said control circuit; and b. a second accumulation register substantially the same in operation and capacity as said first accumulation register, said second accumulation register further operable to be set to 0 count upon receipt of a reset signal, said second accumulation Register disposed to receive pulses from said pulser, to receive reset signals in the form of count pulses from said counting circuit, and to emit pulses to said control circuit whereby the sequence of operations starting from the transmission of c(n) pulses into said first accumulation register results in a count of k in said storage register and a count of r in said second accumulation register.
 6. The device of claim 5 wherein said gate circuit is operable to transmit signals from the pulser to the counting circuit if it receives a bias signal F but to block the transmission of said signals if it receives a bias signal F and wherein the control circuit includes: bias means operatively associated with said gate circuit, said bias means consisting of a flip-flop circuit disposed to receive pulses from both the first and second accumulation registers, wherein said flip-flop circuit can be in only one of two states, F and F, and wherein said bias means is operative to transmit a bias, F or F, to said gate circuit, whereby the sequence of operations starting from the transmission of c(n) pulses into said first accumulation register, said bias means being initially in state F, results in a count of k in said storage register and a count of c(r) in said first accumulation register where c(r) N+1-r.
 7. The device of claim 6 wherein said storage register includes: a plurality of subregisters, each of said subregisters operable to count and record a number k of pulses received by it; a gate network operatively associated with said control circuit and disposed to receive count pulses from said count circuit and direct said count pulses into one selected subregister.
 8. The device of claim 7 wherein the control circuit further includes: digit selection means operatively associated with said gate network and said counting circuit, said digit selection means operative to control the number y of pulses which will cause said counting circuit to emit one count pulse, said digit selection means further operative to cause said gate network to direct said count pulses into one selected subregister.
 9. The device of claim 8 wherein the control circuit further includes: program means operatively associated with said digit selection means, said program means operable to cause said digit selection means to assign successively values of bm to y, where b and m are integers and the exponent m progresses consecutively from a value M to the value 0, where bM is less than N, the capacity of the accumulation register, and where y is the number of pulses which will cause said counting circuit to emit a count pulse, said program means further operable to cause the successive values of k generated to be recorded in successive subregisters, said program means further operable to transmit a delayed stop signal to said pulser when m
 0. 